The invention relates to delay lines in integrated circuits (ICs). More particularly, the invention relates to a delay line trim unit that exhibits consistent performance under varying process and temperature conditions, such trim units being particularly useful in the design of delay-lock loop circuits (DLLs).
Clock signals are used in virtually every IC and electronic system to control timing. For example, every time there is a rising edge on a clock signal, all the flip-flops in a circuit might change state. Clearly, clocks are often heavily loaded signals, and can be bussed throughout a very large IC. Even with specially-designed global buffers, there is typically a delay (a xe2x80x9cclock skewxe2x80x9d) between the clock edge received by the IC at the pad, and the clock edge received by the last-served flip-flop on the IC (i.e., between the xe2x80x9cinput clock signalxe2x80x9d and the xe2x80x9cdestination clock signalxe2x80x9d). This delay can cause difficulties in interfacing between ICs, or can simply slow down the overall system speed.
For example, input data is typically provided in synchronization with an input clock signal, while output data is typically provided in synchronization with a destination clock signal. Further, the skew between the two clock signals often varies not only between different ICs, but on a single IC with temperature and voltage as well. Thus, clock signals are typically synchronized, e.g., using a delay-lock loop circuit (DLL).
FIGS. 1 and 1A illustrate clock skew in a typical IC. FIG. 1 shows an input clock signal GCLK, which is distributed through clock network 101 to provide delayed clock signal DCLK. The delay (skew) between signals GCLK and DCLK is designated as xe2x80x9ctdxe2x80x9d in FIG. 1A. Delay xe2x80x9ctmxe2x80x9d is the amount of time by which signal DCLK would have to be delayed to bring signals DCLK into synchronization with input clock signal GCLK.
FIGS. 2 and 2A illustrate the use of a DLL to synchronize signals DCLK and GCLK. The DLL 201 adds an additional delay xe2x80x9ctmxe2x80x9d to the path between input clock signal GCLK and the output/feedback clock signal, which in FIG. 2 is designated FBCLK. DLL 201 determines the value of delay xe2x80x9ctmxe2x80x9d by comparing the feedback clock signal FBCLK to the input clock signal GCLK, and inserts a delay of xe2x80x9ctmxe2x80x9d into the clock path. Clock network 202 adds additional delay xe2x80x9ctdxe2x80x9d, as in FIG. 1. As a result, when the DLL is enabled and an initial synchronization period has elapsed, feedback clock signal FBCLK is synchronized with input clock signal GCLK, as shown in FIG. 2A. Each clock signal has a period of xe2x80x9ctd+tmxe2x80x9d.
DLLs are well known in the art of IC design. Therefore, detailed DLL implementations are not described herein. However, FIG. 3 shows a block diagram of a common type of DLL. The DLL of FIG. 3 includes a tuneable delay line 301, a trim unit 302, and a control circuit 303. Each of delay line 301 and trim unit 302 delays input signal GCLK, but delay line 301 performs a coarse adjustment (i.e., inserts a relatively larger delay), while trim unit 302 performs a more fine-tuned adjustment (i.e., inserts a relatively smaller delay).
The delay inserted by the trim unit is typically less than twice the minimum delay that can be inserted by delay line 301. For example, the delay inserted by the trim unit can be one unit delay of the delay line plus a small incremental delay of a few tens of picoseconds. Control circuit 303 determines the magnitude of the inserted delays, controlling delay line 301 via select signals SDDL and trim unit 302 via select signals SDTU.
FIG. 4 shows a common implementation of tuneable delay line 301. The delay line of FIG. 4 includes a series of identical delay elements, e.g., inverter pairs (DE 401-404). Each delay element DE 401-404 through which the clock signal passes adds one unit delay to the clock signal. The output signals from the delay elements are tapped and passed to a multiplexer 410, which selects one of the output signals as including a delay closest to the desired delay xe2x80x9ctmxe2x80x9d. Multiplexer 410 is controlled by control circuit 303 via select signals SDDL. The number of delay elements is typically much larger than four, but four delay elements are shown in FIG. 4 for exemplary purposes.
FIG. 5 shows a common implementation of trim unit 302. The delay elements used in the trim unit of FIG. 5 are coupled in parallel rather than in series, and they are not of uniform design. The clock signal driving the trim unit, INTCLK, is passed to each of the delay elements, each of which provides a slightly different delay. The output of each delay element is passed to multiplexer 510, which is controlled by control circuit 303 via select signals SDTU.
DLL circuits can be susceptible to variations in process and temperature, requiring constant adjustment in order to provide a reliable clock signal. These adjustments can cause jitter in the clock signals provided by the DLL circuits. It is desirable to reduce this jitter as much as possible by using DLL sub-circuits that are less sensitive to these variations. Therefore, it is desirable to provide a trim unit for a DLL delay line in which the delays remain balanced in spite of variations in process and temperature.
The invention provides a delay circuit having a delay that is consistent under varying process and temperature conditions. As in the prior art, the delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters (i.e., between the inverters and power high, and between the inverters and ground). However, the various resistors have resistance values that are determined by a number of similarly-sized transistors coupled in parallel across the resistor, rather than by varying the size of a single transistor. Select signals are used to control how many of the transistors are enabled. The total resistance of each plurality of transistors is determined by the number of transistors enabled within each plurality.
A first aspect of the invention provides a delay circuit that includes first and second inverters coupled in series. A plurality of first transistors are coupled in parallel between the first inverter and power high, and a plurality of second transistors are coupled in parallel between the second inverter and power high. Similarly, a plurality of third transistors are coupled in parallel between the first inverter and ground, and a plurality of fourth transistors are coupled in parallel between the second inverter and ground. The transistors within each plurality are all of the same size, and at least two of the transistors within each plurality (i.e., within each resistor) have gate terminals coupled to different select signals. In some embodiments, the sizes of the different pluralities of transistors are all different.
Because all of the transistors within each resistor are of the same size, the total resistance of each resistor varies in a predictable manner with the number of enabled transistors.
In one embodiment, the first and second transistors are P-channel transistors, while the third and fourth transistors are N-channel transistors. Within each plurality of transistors, a first transistor is coupled to power high (for the N-channel transistors) or ground (for the P-channel transistors).
Some embodiments include more than one delay circuit. A second delay circuit includes two inverters and four pluralities of transistors as described above, with an additional delay element on the path through the second delay circuit. These embodiments also include a multiplexer circuit that selects between the output signals from the two (or more) delay circuits. In some of these embodiments, the sizes of the transistors are the same in the different delay circuits.
Another aspect of the invention provides a variable delay line that includes two variable delay elements and a multiplexer circuit that selects between the output signals from the delay circuits. Each variable delay line is implemented substantially as described above.
Yet another aspect of the invention provides a delay-lock loop circuit (DLL) that includes a tuneable delay line and a trim unit circuit coupled in series, and a control circuit. The control circuit controls each of the tuneable delay line and the trim unit circuit. The trim unit circuit is implemented substantially as described above. In one embodiment, in which the DLL forms a portion of a programmable logic device (PLD), the resistor values of the variable delay elements are controlled by select values stored in configuration memory cells, and the multiplexer is controlled by the control circuit to select the output signal from one of the variable delay elements.
Another aspect of the invention provides a PLD that includes first and second configuration memory cells and a delay circuit, the delay circuit substantially as described above. One transistor of each of the first, second, third, and fourth pluralities of transistors has a gate terminal coupled to the first configuration memory cell. Another transistor of each of the first, second, third, and fourth pluralities of transistors has a gate terminal coupled to the second configuration memory cell. Thus, the value stored in the configuration memory cell controls the value of each resistor.